AMD begins Zen5 enablement for GNU Compiler Collection (GCC), new AVX instructions added

AMD begins Zen5 enablement for GNU Compiler Collection (GCC), new AVX instructions added

AMD Zen5 patches for GCC

AMD has begun work on enabling the Zen5 microarchitecture through the GNU Compiler Collection (GCC). First patches were shared through a mailing list titled “Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model”.

One could have expected Zen5 enablement to come sooner, considering that the GCC 14 release is expected in March and April, which is a typical annual release for this compiler. However, AMD tends to release such updates even after the release of the new product. That said, AMD is actually speeding up its enablement by introduction first Zen5 patches even before the product launch.

The Zen5 architecture is expected to make its debut later this year, featuring the desktop Granite Ridge series and potential mobile variants from the Strix Point series. Interestingly, AMD’s progress on Zen5 development is occurring alongside Intel’s work on the Clearwater Forest and Panther Lake CPU series, not expected to launch this year.

Zen5 instruction set, Source: GCC

According to the first patches, AMD Zen5 is confirmed to support new instructions such as AVXVNNI, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI. Some of these instructions are already supported by Intel Tiger Lake series, but were absent in the AMD products until now:

It’s great seeing AVX-512 VP2INTERSECT, which has been found on the Intel side since Tigerlake. MOVDIRI and MOVDIR64B have also been found on the Intel side since Tigerlake. PREFETCHI is exciting and only coming on the Intel side with Granite Rapids. Lastly is AVX-VNNI new to Zen 5 for being equivalent to AVX512-VNNI with VEX encoding.

— Phoronix

The report adds that the same instruction set is listed for the whole family of Zen5 products, which essentially means that Zen5c considered a more power-efficient variant, will support the same instructions.

As this is an initial enablement, certain scheduling code has been ported from Zen4 until AMD engineers provide an updated version. Additionally, there’s an unresolved question regarding the availability of LLVM/Clang compilers for Zen5. Patches for this compiler are yet to be seen.

AMD RYZEN ROADMAP (Based on official and rumored info)
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Threadripper 7000

Chagall

Zen4

TBC

Ryzen 7000

Raphael

Zen4 & RDNA2

Ryzen 7000X3D

Raphael

Zen4X3D & RDNA2

Ryzen

Granite Ridge

Zen5 & RDNA2

Ryzen X3D

Granite Ridge

Zen5X3D & RDNA2

Ryzen 8000G

Phoenix

Zen4/Zen4c & RDNA3

TBC

Ryzen 7000H(X3D)

Dragon Range

Zen4 & RDNA2

Ryzen HX3D

Fire Range

Zen5 & RDNA2

Ryzen

Strix Halo

Zen5/c & RDNA3.5

Ryzen

Strix Point

Zen5/c & RDNA3.5

TBC

Ryzen 6000H

Rembrandt

Zen3+ & RDNA2

Ryzen 7000H

Phoenix

Zen4/c & RDNA3

Ryzen

Kraken Point

Zen4/c & RDNA3

TBC

Source: Phoronix



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